Multi-Dimensional Parallel Rank Order Filtering

M. V. D. Horst, R. H. Mak
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引用次数: 3

Abstract

We present a method to design multi-dimensional rank order filters. Our designs are more efficient than existing ones from literature, e.g. reducing the number of operations required by a 2-dimensional 7 × 7 median filter by 66%. This efficiency is maintained regardless of the amount of parallelism, therefore the throughput of our designs scales linearly with the amount of hardware. To accomplish this we introduce a framework in the form of a generator graph. This graph allows us to formalize our methods and formulate an algorithm that produces efficient designs by reusing common sub-expressions. Like other rank order filters our designs are based on sorting networks composed from Batcher¿s merging networks. However, we introduce an additional optimization that increases the savings obtained by pruning sorting networks. Our design method is independent of the implementation method and resulting designs can be implemented both as a VLSI circuit and as a program for an SIMD processor.
多维并行秩序滤波
提出了一种设计多维秩序滤波器的方法。我们的设计比现有文献中的设计更高效,例如将二维7 × 7中值滤波器所需的操作次数减少了66%。无论并行度多少,这种效率都保持不变,因此我们设计的吞吐量与硬件数量呈线性增长。为了实现这一点,我们引入了一个生成器图形式的框架。这个图允许我们形式化我们的方法,并制定一个算法,通过重用公共子表达式产生有效的设计。与其他秩序过滤器一样,我们的设计基于由Batcher合并网络组成的排序网络。然而,我们引入了一个额外的优化,它增加了通过修剪排序网络获得的节省。我们的设计方法独立于实现方法,结果设计既可以作为VLSI电路实现,也可以作为SIMD处理器的程序实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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