{"title":"Transient thermal imaging characterization of a die attached optoelectronic device on silicon","authors":"K. Yazawa, D. Kendig, K. Al-Hemyari, A. Shakouri","doi":"10.1109/ITHERM.2014.6892431","DOIUrl":null,"url":null,"abstract":"Packaging of optoelectronic devices becomes more and more challenging due to higher heat generation per unit volume. We experimentally investigated the packaging thermal resistance for a semiconductor laser device and compared results for two material alternatives for the electrical passivation layer. We used the time-resolved thermoreflectance technique to obtain the time response for the thermal diffusion. During this investigation, we also discovered another key factor related to the thermal resistance in addition to the passivation layer. The silicon substrate (~700 microns thick) also needs careful consideration for thermal diffusion. We observed some thermal islands across the thickness of the silicon substrate to diffuse and spread the heat. This local anisotropy, however, may be minor as the macroscopic temperature gradient is found to be reasonable. Nevertheless, this localized phenomenon may lead to performance variations in mass production. In the investigated package samples, minor voids and cracks were observed in the copper heat sink area. This may not be anticipated for final manufacturing, but these defects could result in localized higher thermal resistance for some of the arrayed device features on a chip. By using the transient thermoreflectance technique, the heat diffusion process can be observed. This imaging technique enables us to track the temperature over a wide range of time. The time response curve provides an indication of the thermal heat sinking performance of the package structure. The transient thermal response clearly shows two stages of temperature rise. One is the spreading thermal diffusion in the silicon substrate and the other is thermal diffusion into the copper heat sink. The thermal mass for both, is within the time range. In this case, the opposite side of the device of the copper heat sink is connected to the thermal ground with a small thermal resistance. The result demonstrates that a poly silicon passivation layer works better than silicon dioxide and decreases the thermal resistance by almost 30%.","PeriodicalId":12453,"journal":{"name":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","volume":"24 1","pages":"1308-1312"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITHERM.2014.6892431","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Packaging of optoelectronic devices becomes more and more challenging due to higher heat generation per unit volume. We experimentally investigated the packaging thermal resistance for a semiconductor laser device and compared results for two material alternatives for the electrical passivation layer. We used the time-resolved thermoreflectance technique to obtain the time response for the thermal diffusion. During this investigation, we also discovered another key factor related to the thermal resistance in addition to the passivation layer. The silicon substrate (~700 microns thick) also needs careful consideration for thermal diffusion. We observed some thermal islands across the thickness of the silicon substrate to diffuse and spread the heat. This local anisotropy, however, may be minor as the macroscopic temperature gradient is found to be reasonable. Nevertheless, this localized phenomenon may lead to performance variations in mass production. In the investigated package samples, minor voids and cracks were observed in the copper heat sink area. This may not be anticipated for final manufacturing, but these defects could result in localized higher thermal resistance for some of the arrayed device features on a chip. By using the transient thermoreflectance technique, the heat diffusion process can be observed. This imaging technique enables us to track the temperature over a wide range of time. The time response curve provides an indication of the thermal heat sinking performance of the package structure. The transient thermal response clearly shows two stages of temperature rise. One is the spreading thermal diffusion in the silicon substrate and the other is thermal diffusion into the copper heat sink. The thermal mass for both, is within the time range. In this case, the opposite side of the device of the copper heat sink is connected to the thermal ground with a small thermal resistance. The result demonstrates that a poly silicon passivation layer works better than silicon dioxide and decreases the thermal resistance by almost 30%.