Submicron-Scale Cu RDL Pattering Based on Semi-Additive Process for Heterogeneous Integration

T. Takano, H. Kudo, Masaya Tanaka, M. Akazawa
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引用次数: 8

Abstract

Use of dry plasma etching rather than wet etching of a Cu-seed layer in a semi-additive process enabled more precise dimension controllability in the patterning of submicron-scale Cu traces due to no shift in the width of the traces. This controllability is comparable to that of competitive fabrication technologies such as that for damascene-based Cu redistribution layers. The dry etching enabled the patterning of Cu traces with an aspect ratio as high as 4.2 (L/S=0.7/0.7 µm, 3.0 µm in height) without any failures such as electrical shorts between traces. Simulation showed that an increase in the aspect ratio effectively reduced signal transmission loss due to a reduction in conductor loss. The dry etching provided very smooth surfaces on the Cu-trace side-wall (roughness as low as 0.05 µm). This further reduced the signal transmission loss compared to that of wet-etched Cu traces. Submicron-scale patterning of Cu traces using dry etching enables flexible design of redistribution layer lines in terms of signal integrity, in addition to increasing the number of signal I/Os cost effectively.
基于半加性工艺的非均匀集成亚微米尺度Cu RDL图案
在半加性工艺中,使用干等离子体蚀刻而不是湿法蚀刻铜籽层,可以在亚微米尺度的铜迹的图案中实现更精确的尺寸可控性,因为迹的宽度没有变化。这种可控性可与竞争性制造技术相媲美,例如基于大马士革的Cu重分配层。干式蚀刻使铜走线的纵横比高达4.2 (L/S=0.7/0.7µm,高度3.0µm),没有任何故障,如走线之间的电短路。仿真结果表明,宽高比的增加可以有效地降低信号传输损耗,因为导体损耗降低了。干蚀刻在cu痕量侧壁上提供了非常光滑的表面(粗糙度低至0.05µm)。与湿蚀铜走线相比,这进一步降低了信号传输损耗。使用干蚀刻的亚微米尺度的Cu走线图图化,除了可以有效地增加信号I/ o的数量外,还可以在信号完整性方面灵活地设计再分配层线。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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