Multi-scale measurement of the change of the residual stress in a silicon chip during manufacturing from thin-film processing to packaging

H. Kishi, T. Sasaki, N. Ueta, Ken Suzuki, H. Miura
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Abstract

Both thermal and intrinsic stresses that occur during thin-film processing and packaging dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. So, it showed miniaturization of transistors increased the stress sensitivity of the performance. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. Next, the change of the residual stress caused by the interference of the stress concentration field between gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making one slit by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. In addition, the change of residual stress was increased with the more decreased width of slits. It was confirmed, therefore, that both the thin film process-induced stress and the packaging-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.
硅片从薄膜加工到封装过程中残余应力变化的多尺度测量
在薄膜电子器件中,薄膜加工和封装过程中产生的热应力和本征应力主导着最终残余应力。由于残余应力引起介电材料和半导体材料的电子功能的位移,这些位移有时会降低它们的性能和可靠性。因此,对薄膜应用产品的残余应力进行测量和控制是十分重要的。本研究采用四点弯曲法测量了机械应力对MOS晶体管电子性能的影响。当栅极长度从400 nm减小到150 nm时,NMOS晶体管的跨导应力敏感性从约1%/100-MPa增加到约15%/100-MPa。因此,晶体管的小型化提高了性能的应力敏感性。据估计,导致这种增加的重要因素之一是栅极边缘发生的应力集中场的干扰。采用有限元法分析了薄膜沉积对晶体管结构中残余应力的影响。利用最初开发的应力传感芯片,通过实验验证了估计的变化。栅极钨膜沉积引起的应力变化估计约为25MPa。实测平均应力约为20MPa,与估计值吻合较好。其次,应用该应力传感芯片验证了栅极间应力场干扰引起的残余应力变化。结果表明,聚焦离子束形成一条狭缝所引起的应力变化约为70MPa,与60MPa的估计值吻合较好。此外,随着缝宽的减小,残余应力的变化也随之增大。因此,薄膜工艺引起的应力和封装引起的应力都会改变晶体管结构中的最终残余应力,并且这种变化可以通过我们的应力传感芯片定量地评估。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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