Design of Low-Power Memory-Efficient Viterbi Decoder

Abstract

This paper presents a new low-power memory-efficient trace-back (TB) scheme for high constraint length Viterbi decoder (VD). With the trace-back modifications and path merging techniques, up to 50% memory read operations in the survivor memory unit (SMU) can be reduced. The memory size of SMU can be reduced by 33% and the decoding latency can be reduced by 14%. The simulation results show that compared to the conventional TB scheme, the performance loss of this scheme is negligible.