Failure analysis of thermal degradation of TIM during power cycling

Abstract

This paper discusses a thermal reliability testing experiment and failure analysis (FA) in 32nm SOI Si technology chip packages. Thermal performance of the TIM materials is monitored and physical failure analysis is performed on test vehicle packages post thermal reliability test. Thermomechanical modeling is conducted for different test conditions. TIM thermal degradation is observed at the chip center area in the batch of samples post power cycling (PC) test, while the TIM performance remains normal in the other batch of samples post thermal aging (TA) test. Physical FA findings after TIM bond line thickness measurement (at the chip corners and chip center) and unlidding to inspect the TIM surface morphology confirmed the failure mode is TIM to chip tearing. Finite element modeling results indicate significant difference of stress status in TIM and sealband adhesive between PC and TA test. The TIM experiences compressive stress during PC test, while it is in tensile stress during TA test.