A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs

Abstract

A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔIDLIN) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (VD), gate (VG) and body (VBB) biases is modeled. The framework is also capable of modeling the channel length (LCH) and gate-oxide thickness (TOX) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔIDLIN modeling.