Advanced methodology for assessing chip package interaction effects on chip performance and reliability after chip assembly and during chip operation

Abstract

An advanced multiphysics EDA (Electronic Design Automation) methodology is presented for analyzing thermal and thermomechanical problems during chip assembly and operation. The tool-prototype, which was built on the basis of this methodology, employs an anisotropic effective thermal-mechanical property methodology that replaces building complex geometries in finite element analysis simulations, thereby enhancing accuracy and performance significantly. With multiscale capabilities enabled, the tool-prototype first performs full chip stress and temperature analyses and detects hotspots. Then, a detailed analysis is performed in the selected regions of interest, with the resolution adjusted to a feature-scale by adopting a finer grid for extracting effective properties, and enables one to address feature-scale stress-induced issues such as back-end-of-line cracking or stress-induced mobility degradation of transistors. When the tool-prototype is linked with power analysis and layout EDA tools, it can perform the reliability check within the design flow. The assessment procedure will help to design power efficient chips by avoiding thermal and stress hotspots that compromise chip performance and reliability.