Pulse Width Modulated Cascaded Multi Level Inverter Topology

Abstract

In this paper a new cascaded multi level inverter is proposed. It consists of a basic module which can generate fifteen level output considering zero level. PWM switching scheme is used here for generating the pulses for the switches in the proposed topology. This topology shows the advantages over some of existing topology reported in the literature in respect of number of switches, drivers, sources etc. It can also be applied for symmetric as well as asymmetric configuration. Validation of the proposed topology has been ascertained by simulation in Matlab environment and hardware set up has been developed for fifteen level multi level inverter. Hardware and simulation results are in close agreement with each other.