Selective Barrier for Cu Interconnect Extension in 3nm Node and Beyond

Abstract

The continued scaling in logic technology poses significant challenges such as huge resistance-capacitance (RC) delays due to the shrinkage in dimensions. To address the BEOL Cu interconnect portion of RC delays, reducing the via resistance through Tantalum Nitride (TaN) barrier layer adjustment is critical while in the meantime must meet the reliability requirement. TaN barrier on via bottom contribute the major portion of Via R due to its high resistivity. Thinner TaN barrier approach, however, is limited due to its degraded barrier performance; In this paper, we presented the study of selective barrier approach that utilize gas phase metal passivation method to provide barrier free via bottom. >50% via R reduction is demonstrated with no reliability degradation.