UltraScale+ MPSoC and FPGA families

V. Boppana, Sagheer Ahmad, I. Ganusov, Vinod Kathail, V. Rajagopalan, Ralph Wittig
{"title":"UltraScale+ MPSoC and FPGA families","authors":"V. Boppana, Sagheer Ahmad, I. Ganusov, Vinod Kathail, V. Rajagopalan, Ralph Wittig","doi":"10.1109/HOTCHIPS.2015.7477457","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation. Zynq UltraScale+ MPSoC: 2nd Generation SoC from Xilinx - Applications processing, Real-time, Graphics, Video, Serial connectivity - Power management, Safety, Security - SDSoC: Full system optimizing compiler; More than Moore: Architectural innovation - 3x CPU performance and 4.5x memory bandwidth (SoC) -UltraScale+ fabric: 60% higher performance, 2.5x performance/watt (FPGA) - 3rd generation of silicon interposer technology (3D IC); Taped out in Jun 2015 on TSMC 16FF+ - Significant power and performance benefits with 3D FinFet transistors - Diverse SW and systems running on multiple platforms today.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"145 1","pages":"1-37"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"32","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2015.7477457","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 32

Abstract

This article consists of a collection of slides from the authors' conference presentation. Zynq UltraScale+ MPSoC: 2nd Generation SoC from Xilinx - Applications processing, Real-time, Graphics, Video, Serial connectivity - Power management, Safety, Security - SDSoC: Full system optimizing compiler; More than Moore: Architectural innovation - 3x CPU performance and 4.5x memory bandwidth (SoC) -UltraScale+ fabric: 60% higher performance, 2.5x performance/watt (FPGA) - 3rd generation of silicon interposer technology (3D IC); Taped out in Jun 2015 on TSMC 16FF+ - Significant power and performance benefits with 3D FinFet transistors - Diverse SW and systems running on multiple platforms today.
UltraScale+ MPSoC和FPGA系列
本文由作者在会议上演讲的幻灯片集合组成。Zynq UltraScale+ MPSoC:赛灵思第二代SoC -应用处理,实时,图形,视频,串行连接-电源管理,安全,安全- SDSoC:全系统优化编译器;超越摩尔:架构创新- 3倍CPU性能和4.5倍内存带宽(SoC) - ultrascale +结构:性能提高60%,2.5倍性能/瓦(FPGA) -第三代硅中间体技术(3D IC);2015年6月在TSMC 16FF+上录制- 3D FinFet晶体管的显著功率和性能优势-今天在多种平台上运行的各种软件和系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信