{"title":"Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression","authors":"G. Pastuszak","doi":"10.1109/SIPS.2007.4387540","DOIUrl":null,"url":null,"abstract":"The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binarization unit, which is a part of the last stage of the video coder. The module supports CABAC and CAVLC modes and conforms to H.264/AVC High Profile. The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. For both modes, the architecture achieves the similar throughput able to support HDTV.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"2640 1","pages":"175-180"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2007.4387540","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binarization unit, which is a part of the last stage of the video coder. The module supports CABAC and CAVLC modes and conforms to H.264/AVC High Profile. The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. For both modes, the architecture achieves the similar throughput able to support HDTV.
硬件视频编码器的效率取决于处理路径中嵌入的所有模块。本文介绍了H.264/AVC二值化单元的结构,该单元是视频编码器最后阶段的一部分。该模块支持CABAC和CAVLC模式,符合H.264/AVC High Profile标准。由于两种编码模式共享相同的逻辑和存储元素,因此该体系结构节省了大量硬件资源。对于这两种模式,该架构实现了相似的吞吐量,能够支持HDTV。