Enhanced overloaded code division multiple access for network on chip

IF 1.1 4区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IET Computers and Digital Techniques Pub Date : 2021-12-07 DOI:10.1049/cdt2.12039

Behnam Vakili, Morteza Gholipour

引用次数: 1

Abstract

The Code-division multiple access (CDMA) method is commonly used as the network infrastructure in multi-core chips. One of its advantages is the simultaneous connection of all network components. Another advantage is the constant delay of this method. On the other hand, one drawback is that the number of transmitters is limited to the number of encoding bits. In this study, the authors used the combination of Walsh codes and their inverses, as well as the simultaneous application of the time-division multiple access (TDMA) method, to increase the transmission capacity of this protocol more than four times the standard mode. In the proposed design, although the circuit area does not increase significantly, a fourfold increase in the throughput of the CDMA network is seen. Using the method proposed in this study, it will be possible to increase the capacity further.

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片上网络的增强型重载码分多址

码分多址(CDMA)方式是多核芯片中常用的网络基础设施。它的优点之一是所有网络组件的同时连接。这种方法的另一个优点是延时不变。另一方面，一个缺点是发射机的数量受限于编码位的数量。在本研究中，作者利用沃尔什码及其逆码的组合，以及时分多址(TDMA)方法的同时应用，使该协议的传输容量比标准模式增加了四倍以上。在提出的设计中，虽然电路面积没有显著增加，但CDMA网络的吞吐量增加了四倍。使用本研究提出的方法，将有可能进一步提高容量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IET Computers and Digital Techniques 工程技术-计算机：理论方法

CiteScore

3.50

自引率

0.00%

发文量

审稿时长

>12 weeks

期刊介绍： IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.