Low-Loss Additively-Deposited Ultra-Short Copper-Paste Interconnections in 3D Antenna-Integrated Packages for 5G and IoT Applications

A. Watanabe, Yiteng Wang, N. Ogura, P. Raj, V. Smet, M. Tentzeris, R. Tummala
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引用次数: 5

Abstract

High-bandwidth 5G and 6G communication systems will inevitably migrate to 3D package architectures with backside or embedded dies and antenna-integrated packages for ultra-low losses and smaller footprints. With the trend to such 3D millimeter-wave (mm-wave) packages, the losses from the assembly and through-vias tend to dominate the overall losses. Traditional wirebond and thick solder interconnections lead to large mm-wave interconnect losses that are not acceptable for emerging 5G and 6G communications. This paper focuses on the material syntheses and process development of nanocopper interconnections with ultra-low interconnect losses for chip-last or flip-chip assembly in packages. The first part of the paper introduces the material synthesis of an innovative copper paste with shorter sintering times and temperatures. Optimized conditions are obtained to attain a conductivity of 1.4x10^7 S/m. This is equivalent to 82% increase in conductivity compared to that of solder. The surface roughness is also measured through atomic-force microscopy. Results suggest that the copper paste features higher roughness than that of solders. The second part of this paper discusses the potential of novel nanocopper paste to replace solders as a package assembly material, focusing on the effect of the conductivity and surface roughness with regard to the insertion loss in interconnection bumps. Based on the improved material properties of nanocopper paste, the model shows a 53% reduction in the dB scale at 28 GHz, by employing nanocopper paste. Die shear test for copper paste is also performed to show a high potential to replace solders as a flip-chip assembly material in both printed-circuit-board and mm-wave packaging technologies.
用于5G和物联网应用的3D天线集成封装中的低损耗加积超短铜膏互连
高带宽5G和6G通信系统将不可避免地迁移到具有背面或嵌入式芯片和天线集成封装的3D封装架构,以实现超低损耗和更小的占地面积。随着这种3D毫米波封装的趋势,组装和通孔的损耗往往占总损耗的主导地位。传统的线键和厚焊互连会导致巨大的毫米波互连损耗,这对于新兴的5G和6G通信来说是不可接受的。本文重点研究了超低互连损耗纳米铜互连材料的合成和工艺发展,用于芯片内组装或倒装封装。本文第一部分介绍了一种烧结时间短、烧结温度低的新型铜膏的材料合成。得到了电导率为1.4 × 10^7 S/m的优化条件。这相当于与焊料相比电导率增加82%。表面粗糙度也通过原子力显微镜测量。结果表明,铜膏体的粗糙度高于焊料。本文的第二部分讨论了新型纳米铜膏取代焊料作为封装组装材料的潜力,重点讨论了电导率和表面粗糙度对互连凸点插入损耗的影响。基于纳米铜浆料材料性能的改善,模型显示,纳米铜浆料在28 GHz时的dB尺度降低了53%。铜膏体的模具剪切测试也显示出在印刷电路板和毫米波封装技术中取代焊料作为倒装芯片组装材料的高潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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