FPGA Implementations of LDPC over GF(2m) Decoders

Abstract

Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.