Modeling of interconnect stress evolution during BEOL process and packaging

Abstract

A novel simulation approach is developed to examine the stress evolution in the chip-to-package interconnect structures during the sequential IC Backend processes followed by packaging / assembly operation. Packaging induced stress in near-bump and BEOL level models is examined using the multi-level FEA methodology. Likewise, the Backend process induced stresses in the interconnect structures is analyzed using a sequential process simulation that looks into stress evolution of the BEOL structure as each metal-dielectric layer is being patterned. Finally, the cumulative impact of packaging induced stress and the BEOL process induced stress on the interconnect structures is examined to demonstrate the significance of this approach in performing a “design dependent” CPI risk analysis for BEOL interconnects.