VLSI implementation of dynamically reconfigurable hardware-based cryptosystem

Abstract

A cipher core has been implemented, which is dedicated to the 64-bit block, 128-bit key novel hardware-based cryptosystem called Chameleon. Chameleon adopts the approach that is distinctive for its two 32-cell, 8-context dynamically reconfigurable unit to generate subkeys for each of the 16 iterations of encryption process. The proposed cipher core has been integrated in the die area of 5.90 mm/sup 2/ by means of a 0.6 /spl mu/m CMOS 3 LM technology which attains a maximum throughput of 635 Mbps.