A Fast Calculation Model for Parasitic Inductance of SiC Power Devices

Abstract

Silicon carbide (SiC) power device has a leap forward improvement in various performance indexes compared with the existing silicon-based power devices, and is suitable for higher frequency working occasions. Its high switching speed makes it more sensitive to stray parameters and easier to cause voltage and current oscillation. Therefore, reducing the inductance of power module has become the key to module design. Usually when designing the layout of the power module, it is necessary to establish the 3d model and then use the Q3d software to extract the internal circuit inductance of the device. The process is complicated and the design cycle is long. To solve this problem, this article focuses on the rapid evaluation method of loop inductance in the process of power module layout design, and proposes a faster, simpler, and relatively accurate calculation model based on the existing theories - Inductance Calculation Model of Arbitrary Shape Open-loop Circuit. Then, the convenience and accuracy of the equivalent closed loop model are verified by calculating three different IGBT layout loop inductances. This method is conducive to the rapid iteration of the power module layout design and shortens the design cycle.