A 12 b 105 Msample/s, 850 mW analog to digital converter

Abstract

This analog-to-digital converter achieves a minimum sampling rate of 105 Msample/S at a total power dissipation of 850 mW while achieving 11.0 effective number of bits (SNR=68 dB) and an SFDR of >80 dB for sampling analog input frequencies up to 70 MHz. The converter uses a switched capacitor multi-bit per stage architecture and incorporates an on-chip differential input buffer, a dedicated track/hold amplifier and an internally compensated wideband differential reference amplifier. The converter is fabricated on a 0.6 /spl mu/m BiCMOS process.