Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC

V. Sundaram, Q. Chen, Y. Suzuki, G. Kumar, Fuhan Liu, R. Tummala
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引用次数: 39

Abstract

This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.
低成本和低损耗的3D硅中间体,用于高带宽逻辑到存储器互连,在逻辑IC中没有TSV
本文介绍了一种低损耗、低成本的非传统硅中间体的设计、制造和电学特性,展示了3D硅中间体的高带宽片对片互连能力,其性能与带有tsv的3D集成电路相当或更好,成本低得多。这种可扩展的方法使用晶圆或面板形式的薄多晶硅,通过特殊的高通量激光工艺在细间距上形成低成本的通封装通孔(TPVs)。电性能得到改善的厚聚合物衬里的TPVs。与单面TSV和BEOL晶圆工艺相比,使用干膜聚合物和电镀的TPV金属化和RDL层的双面封装工艺可显着降低成本。低损耗硅中间体中3mm长的CPW线和两个TPVs的综合损耗在10GHz时小于1dB。这种非传统硅中间体的细间距TPV能力和低损耗导致具有双面芯片的3D中间体以同等带宽与宽总线I/O 3D ic互连,成本低得多,具有更好的可测试性,热管理和可扩展性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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