N. Collaert, A. Alian, A. Banerjee, Vikas Chauhan, R. ElKashlan, B. Hsu, M. Ingels, A. Khaled, K. Vondkar Kodandarama, B. Kunert, Y. Mols, U. Peralagu, V. Putcha, R. Rodriguez, A. Sibaja-Hernandez, E. Simoen, A. Vais, A. Walke, L. Witters, S. Yadav, H. Yu, M. Zhao, P. Wambacq, B. Parvais, N. Waldron
{"title":"From 5G to 6G: will compound semiconductors make the difference?","authors":"N. Collaert, A. Alian, A. Banerjee, Vikas Chauhan, R. ElKashlan, B. Hsu, M. Ingels, A. Khaled, K. Vondkar Kodandarama, B. Kunert, Y. Mols, U. Peralagu, V. Putcha, R. Rodriguez, A. Sibaja-Hernandez, E. Simoen, A. Vais, A. Walke, L. Witters, S. Yadav, H. Yu, M. Zhao, P. Wambacq, B. Parvais, N. Waldron","doi":"10.1109/ICSICT49897.2020.9278253","DOIUrl":null,"url":null,"abstract":"In this work, we will address the opportunities of a hybrid III-V/CMOS technology for next generation wireless communication, beyond 5G, moving to operating frequencies above 100GHz. Challenges related to III-V upscaling and CMOS co-integration using 3D technologies will be discussed.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"23 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT49897.2020.9278253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this work, we will address the opportunities of a hybrid III-V/CMOS technology for next generation wireless communication, beyond 5G, moving to operating frequencies above 100GHz. Challenges related to III-V upscaling and CMOS co-integration using 3D technologies will be discussed.