Vertical InAs nanowire MOSFETs with IDS = 1.34 mA/µm and gm = 1.19 mS/µm at VDS = 0.5 V

Abstract

III-V MOSFETs are currently considered for extension of, or as an add-on to, the Si CMOS technology. Following the Si-technology evolution, it is attractive to consider advanced III-V transistor architectures with non-planar geometry and improved electrostatic control. We report on vertical InAs single nanowire FETs with diameter of 45 nm diameter, integrated on Si substrates with LG = 200 nm. The devices demonstrate normalized extrinsic gm and IDS of 1.34 S/mm and 1.19 A/mm, respectively, at a VDS of 0.5 V, and with an onresistance of 321 Ωμm, all values normalized to the circumference. The main performance limitation is identified as the drain resistance in the ungated top part of the wire. By scaling the NW diameter to 28 nm, we also observe subthreshold swing down to 80 mV/decade at 50 mV VDS. However, the on-resistance increases for the narrow wires to 75 kΩμm, and the normalized current level is reduced as compared to the larger diameter wires.