External Power Gating Technique – An Inappropriate Solution for Low Power Devices

Abstract

This paper presents an in-sight about one of the most widely used power optimization technique: a power gating. The power gating technique has been used for use cases, where part of a system is required to be (temporally) disconnected from a power source to reduce the overall system's power consumption. However, we discovered an issue which makes a discrete variant (external MOSFET transistors in power supply paths of an integrated circuit) of the power gating technique unsuitable for low power designs such as battery-operated IoT (Internet of Things) nodes.