Gate bias induced heating effect and implications for the design of deep submicron ESD protection

Abstract

This paper presents a detailed investigation of the degradation of ESD strength with gate bias for various deep submicron ESD protection designs. It has been shown for the first time that gate bias induced heating is the primary cause of this degradation. It has also been established that substrate biasing can help eliminate the negative impact of the gate bias effect, which has significant implications for the design of ESD protection circuits in deep submicron technologies.