Study to Lower Cu Pillar Flip-Chip Failure Rate

Abstract

Cu pillar flip-chip die technology has proved reliable and is widely used in chip-to-package mobile module products. There was a time when customers considered 500ppm (Parts per million) an acceptable defect rate. Now, tier 1 customers expect a defect rate of less than 50ppm. This high customer expectation drove this in-depth research and problem solve. Our main work includes: 1) Mapping and analyzing initial defects. 2) Developing an effective way to detect a low defect rate. 3) 3D mechanical modeling that focuses on multiple failure interfaces and modes. 4) Simulating stress factors and their impacts. 5) Verifying hypothesis with assembly design of experiment (DOE) and ultimately improved yield.