{"title":"Q-scheduler: A temperature and energy-aware deep Q-learning technique to schedule tasks in real-time multiprocessor embedded systems","authors":"Mahsa Mohammadi, Hakem Beitollahi","doi":"10.1049/cdt2.12044","DOIUrl":null,"url":null,"abstract":"<p>Reducing energy consumption under processors' temperature constraints has recently become a pressing issue in real-time multiprocessor systems on chips (MPSoCs). The high temperature of processors affects the power and reliability of the MPSoC. Low energy consumption is necessary for real-time embedded systems, as most of them are portable devices. Efficient task mapping on processors has a significant impact on reducing energy consumption and the thermal profile of processors. Several state-of-the-art techniques have recently been proposed for this issue. This paper proposes Q-scheduler, a novel technique based on the deep Q-learning technology, to dispatch tasks between processors in a real-time MPSoC. Thousands of simulated tasks train Q-scheduler offline to reduce the system's power consumption under temperature constraints of processors. The trained Q-scheduler dispatches real tasks in a real-time MPSoC online while also being trained regularly online. Q-scheduler dispatches multiple tasks in the system simultaneously with a single process; the effectiveness of this ability is significant, especially in a harmonic real-time system. Experimental results illustrate that Q-scheduler reduces energy consumption and temperature of processors on average by 15% and 10%, respectively, compared to previous state-of-the-art techniques.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"16 4","pages":"125-140"},"PeriodicalIF":1.1000,"publicationDate":"2022-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12044","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12044","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 2
Abstract
Reducing energy consumption under processors' temperature constraints has recently become a pressing issue in real-time multiprocessor systems on chips (MPSoCs). The high temperature of processors affects the power and reliability of the MPSoC. Low energy consumption is necessary for real-time embedded systems, as most of them are portable devices. Efficient task mapping on processors has a significant impact on reducing energy consumption and the thermal profile of processors. Several state-of-the-art techniques have recently been proposed for this issue. This paper proposes Q-scheduler, a novel technique based on the deep Q-learning technology, to dispatch tasks between processors in a real-time MPSoC. Thousands of simulated tasks train Q-scheduler offline to reduce the system's power consumption under temperature constraints of processors. The trained Q-scheduler dispatches real tasks in a real-time MPSoC online while also being trained regularly online. Q-scheduler dispatches multiple tasks in the system simultaneously with a single process; the effectiveness of this ability is significant, especially in a harmonic real-time system. Experimental results illustrate that Q-scheduler reduces energy consumption and temperature of processors on average by 15% and 10%, respectively, compared to previous state-of-the-art techniques.
期刊介绍:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.