Y.M. Park, J. Lee, M. Kim, M.K. Choi, K. Kim, J.I. Han, D. Kwon, W. Lee, Y. Song, K. Suh
{"title":"The mechanical stress effects on data retention reliability of NOR flash memory","authors":"Y.M. Park, J. Lee, M. Kim, M.K. Choi, K. Kim, J.I. Han, D. Kwon, W. Lee, Y. Song, K. Suh","doi":"10.1109/IEDM.2001.979611","DOIUrl":null,"url":null,"abstract":"The mechanical stress of silicon nitride and silicon oxynitride, used as gate transistor sidewall or passivation layers in NOR flash memory cells, on data retention characteristics is investigated. The stress is studied by simulation based on experimental data. As the mechanical stress on the floating gate increases, the Vth shift of the programmed cell after bake increases. It is explained by the trap assisted tunneling model. Such stress has a severe impact on data retention when using silicon nitride as the gate sidewall layer and increasing the thickness of it. It is certified that the effect of the passivation layer on data retention is due to the hydrogen concentration in the layer rather than mechanical stress.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"38 1","pages":"32.4.1-32.4.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979611","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
The mechanical stress of silicon nitride and silicon oxynitride, used as gate transistor sidewall or passivation layers in NOR flash memory cells, on data retention characteristics is investigated. The stress is studied by simulation based on experimental data. As the mechanical stress on the floating gate increases, the Vth shift of the programmed cell after bake increases. It is explained by the trap assisted tunneling model. Such stress has a severe impact on data retention when using silicon nitride as the gate sidewall layer and increasing the thickness of it. It is certified that the effect of the passivation layer on data retention is due to the hydrogen concentration in the layer rather than mechanical stress.