A H.264/AVC Quarter-Pixel Motion Estimation Refinement architecture targeting high resolution videos

Abstract

This paper presents a hardware design for the H.264/AVC Quarter-Pixel Motion Estimation Refinement to be used in a complete Fractional Motion Estimation architecture. The architecture was optimized to reach a high throughput through a balanced pipeline and parallelism exploration. The design was described in VHDL and synthesized to an Altera Stratix III FPGA device. The design achieves an operation frequency of 245 MHz, processing up to 39 QHDTV frames (3840×2048 pixels) per second. This architecture is also able to reach real time when processing other resolutions, like HD 1080p (1920×1080 pixels) with lower operation frequencies. The final results are very competitive when compared to related works.