Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology

R. Dunne, Yoshimi Takahashi, Kazuaki Mawatari, Masamitsu Matsuura, Tom Bonifield, Philipp Steinmann, D. Stepniak
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引用次数: 26

Abstract

To enable the miniaturization, electrical performance and heterogeneous functionality needs for emerging Analog applications, a stacked Wafer-level Chip Scale Package (WCSP) package platform has been developed using Through-Silicon Via (TSV) technology. This allows stacking of ICs, MEMS, passives and other components in the vertical direction onto active or passive TSV wafers, to create innovative System-in-Package (SiP) product solutions. Since Analog devices are small in size and cost is a key care about, a careful selection of the integration flow is required to achieve a low cost packaging solution. In this work, an integration flow for the stacked WCSP package is presented, along with development details for the Chip-on-Wafer (CoW) bonding and wafer overmolding unit processes. The test vehicle was 3mm × 3mm in size and used 25u diameter Cu TSVs in a 200mm diameter wafer. Interconnect reliability evaluations were done with different micro-bump Under Bump Metallurgy (UBM) and TSV tip surface finish metallization combinations. Wafer ovemolding development included warpage, saw and adhesion evaluations with multiple mold materials. A back-end assembly flow was established with a mass reflow bonding process and an overmold material with low CTE and intermediate Tg and modulus. Samples were prepared with mold-on-die and exposed die package structures. Excellent time-zero yields were obtained, with an average TSV micro-bump interconnect resistance of 25 mohms. Results and failures modes from preliminary reliability testing are included.
采用TSV (Through Silicon Via)技术的堆叠式WCSP封装平台的开发
为了满足新兴模拟应用的小型化、电气性能和异构功能需求,采用通硅通孔(TSV)技术开发了堆叠晶圆级芯片规模封装(WCSP)封装平台。这允许在垂直方向上将ic, MEMS,无源和其他组件堆叠到有源或无源TSV晶圆上,以创建创新的系统级封装(SiP)产品解决方案。由于模拟器件体积小,成本是一个关键问题,因此需要仔细选择集成流程以实现低成本封装解决方案。在这项工作中,提出了堆叠WCSP封装的集成流程,以及芯片上晶圆(CoW)键合和晶圆覆盖成型单元工艺的开发细节。试验车辆尺寸为3mm × 3mm,在直径200mm的晶圆上使用25u直径的Cu tsv。采用不同的微碰撞冶金(UBM)和TSV尖端表面金属化组合对互连可靠性进行了评估。晶圆复模发展包括翘曲,锯和粘合评估与多种模具材料。采用低CTE、中等Tg和模量的复模材料,建立了大规模回流粘接工艺的后端装配流程。采用模对模和外露模封装结构制备样品。获得了优异的时间零产率,平均TSV微碰撞互连电阻为25 mohm。包括初步可靠性试验的结果和失效模式。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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