Experimentally Minimizing the Gap Distance Between Extra Tall Packages and PCB Using the Digital Image Correlation (DIC) Method

Abstract

The stacked 3D packaging is a trend in current electronic packaging field. The stacked dies are molded to insulate the functional chips from the moisture or the dust. To achieve electrical performance or cost benefits, potential 3D integration schemes that were developed vertically may cause cruel reliability issues, like warpage. For an 8 × 8 × 6 mm3 Wafer Level Package (WLP), the warpage behavior at the top surface cannot comprehensively represent the package deformation since the considerable height change between the PCB and the component's surface, To investigate the solder reliability one indirect way is to observe the relative height change from the edges or the corners of the top surface to the bottom PCB or substrate surface. In this case, the closer the two data points we select-one on the surface component and another on the substrate-the clearer situation it will illustrate. However, there is a gap between those points since the shadow and blind areas caused by the light source and camera angle. Hence, reducing the gap distance is a major concern. In this work, an experimental study on minimizing this gap between a wafer-level-chip-scale-package, (8mm× 8 mm with 6mm and 4 mm heights), and PCB were accomplished with the digital image correlation (DIC) technique. Key factors such as camera angle, white light source, sample orientation, and the subset size and step were studied and experimentally optimized to achieve accurate results. These optimal parameters were aimed to keep the gap distance less than 0.5mm during the extra tall packages measurement.