A bit-line leakage compensation scheme for low-voltage SRAM's

Abstract

The bit-line leakage current of an SRAM, induced by transistor leakage at low V/sub DD/ and dependent on cell data associated with the bit-line, is detected in a pre-charge cycle and compensated for during a read/write cycle. By this scheme, V/sub th/ can be lowered to 0.23 V/sub DD/ in a 0.07 /spl mu/m/1.0 V CMOS, as it was before, keeping V/sub th/ and delay scalability of the high-speed SRAM.