Silicon Oxide Passivation of Single-Crystalline CVD Diamond Evaluated by the Time-of-Flight Technique

K. Kovi, S. Majdi, M. Gabrysch, J. Isberg
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引用次数: 6

Abstract

Diamond is a promising semiconductor material for high power, high voltage, high temperature and high frequency applications due to its remarkable material properties: it has the highest thermal conductivity, it is the hardest material, chemically inert, radiation hard and has the widest transparency in the electromagnetic spectrum. It also exhibits excellent electrical properties like high breakdown field, high mobilities and a wide bandgap. Hence, it may find applications in extreme conditions out of reach for conventional semiconductor materials, e.g. in high power density systems, high temperature conditions, automotive and aerospace industries, and space applications. With the recent progress in the growth of high purity single-crystalline CVD diamond, the realization of electronic devices is now possible. Natural and HPHT diamonds inevitably have too high a concentration of impurities and defects for electrical applications. To develop efficient electronic devices based on diamond, it is crucial to understand charge transport properties. Time-of-flight is one of the most powerful methods used to study charge transport properties like mobility, drift velocity and charge collection efficiency in highly resistive semiconductors, such as diamond. For commercial diamond devices to become a reality, it is necessary to have an effective surface passivation since the passivation determines the ability of a device to withstand high surface electric fields. Surface passivation studies on intrinsic SC-CVD diamond using materials like silicon oxide, silicon nitride and high-k materials have been conducted and observations reveal an increase in measured hole mobilities. Planar MOS capacitor structures form the basic building block of MOSFETs. Consequently, the understanding of MOS structures is crucial to make MOSFETs based on diamond. Planar MOS structures with aluminum oxide as gate dielectric were fabricated on boron doped diamond. The phenomenon of inversion was observed for the first time in diamond. In addition, low temperature hole transport in the range of 10-80 K has been investigated and the results are used to identify the type of scattering mechanisms affecting hole transport at these temperatures.To utilize the potential of diamonds properties and with diamond being the hardest and most chemically inert material, new processing technologies are needed to produce devices for electrical, optical or mechanical applications. Etching of diamond is one of the important processing steps required to make devices. Achieving an isotropic etch with a high etch rate is a challenge. Semi-isotropic etch profiles with smooth surfaces were obtained by using anisotropic etching technique by placing diamond samples in a Faraday cage and etch rates of approximately 80 nm/min were achieved.Valleytronics, which is a novel concept to encode information based on the valley quantum number of electrons has been investigated for the first time in diamond. Valley-polarized electrons with the longest relaxation time ever recorded in any material (300 ns) were observed. This is a first step towards demonstrating valleytronic devices.
用飞行时间技术评价单晶CVD金刚石的氧化硅钝化
金刚石是一种很有前途的高功率、高电压、高温和高频应用的半导体材料,因为它具有显著的材料特性:它具有最高的导热性,它是最硬的材料,化学惰性,辐射硬,并且在电磁波谱中具有最广泛的透明度。它还具有优异的电学性能,如高击穿场,高迁移率和宽带隙。因此,它可能会在传统半导体材料无法达到的极端条件下应用,例如高功率密度系统,高温条件,汽车和航空航天工业以及空间应用。随着近年来高纯度单晶CVD金刚石的发展,电子器件的实现已成为可能。天然钻石和高温高温钻石不可避免地具有过高的杂质浓度和缺陷,无法用于电气应用。为了开发基于金刚石的高效电子器件,了解电荷输运性质至关重要。飞行时间是研究高阻半导体(如金刚石)中迁移率、漂移速度和电荷收集效率等电荷传输特性最有效的方法之一。为了使商用金刚石器件成为现实,必须进行有效的表面钝化,因为钝化决定了器件承受高表面电场的能力。使用氧化硅、氮化硅和高k材料对本征SC-CVD金刚石进行了表面钝化研究,观察结果表明,测量的孔迁移率有所增加。平面MOS电容结构构成了mosfet的基本组成部分。因此,了解MOS结构对于制作基于金刚石的mosfet至关重要。在掺硼金刚石上制备了以氧化铝为栅介质的平面MOS结构。在金刚石中首次观察到反转现象。此外,研究了10-80 K范围内的低温空穴输运,并利用结果确定了影响该温度下空穴输运的散射机制类型。由于金刚石是最坚硬和最具化学惰性的材料,为了利用金刚石特性的潜力,需要新的加工技术来生产用于电气、光学或机械应用的设备。金刚石的蚀刻是制造器件所需的重要加工步骤之一。实现具有高蚀刻速率的各向同性蚀刻是一个挑战。利用各向异性刻蚀技术,将金刚石样品置于法拉第笼中,获得了表面光滑的半各向同性刻蚀轮廓,刻蚀速率约为80 nm/min。谷电子学是一种基于电子谷量子数进行信息编码的新概念,首次在金刚石中得到研究。观察到的谷极化电子弛豫时间是所有材料中最长的(300 ns)。这是演示谷电子器件的第一步。
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来源期刊
ECS Solid State Letters
ECS Solid State Letters MATERIALS SCIENCE, MULTIDISCIPLINARY-PHYSICS, APPLIED
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