NBTI detection methodology for building tolerance with respect to NBTI effects employing adaptive body bias

S. Narang, A. Srivastava
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引用次数: 5

Abstract

The nanometre technology is different fundamentally from its predecessors as it is exposed to a wide variety of new effects that are induced on the transistor chips. NBTI is one degradation effects in the reliability regime. It plays significant role as it leads to severe performance degradation. Ageing in pMOS transistor takes place due to Negative bias temperature instability (NBTI) which is the major threat to reliability as we scale down the transistor geometries consistently towards our objective for less power consumption coupled with high performance. The work presented in this paper focuses on NBTI detection scheme for building tolerance with respect to NBTI effects employing Adaptive Body Bias (ABB). In this scheme, an On-Chip monitor detects the change in threshold voltage of the circuit to generate corresponding adaptive body bias by the body biasing circuit which is supplied to the transistors. The simulations have been carried out taking VBB as zero, i.e., No Body Bias (NBB), by applying a finite adaptive body bias (ABB) voltage to the transistors on the chip & their corresponding power and delay have thus been calculated by implementation of the proposed approach on a host of domino logic circuits which include Current comparison domino (CCD). We have mitigated the rise in delay problem by suitably allocating a supply voltage so that the delay specifications are continuously met even after a time span of 10 years of operation at the cost of very low power headroom. Simulations have been performed using the BSIM4v4.7 model & 32-nm predictive technology model in SILVACO EDA tool at a frequency of 2 GHz and nominal supply voltage of 0.9V. The proposed approach has been implemented on 32-bit & 64-bit OR gates and also on 32-bit comparator and the results has been noteworthy.
利用适应性身体偏差建立NBTI效应耐受性的NBTI检测方法
纳米技术从根本上不同于它的前辈,因为它暴露在晶体管芯片上产生的各种各样的新效应中。NBTI是可靠性体系中的一种退化效应。它起着重要的作用,因为它会导致严重的性能下降。pMOS晶体管的老化是由于负偏置温度不稳定性(NBTI),这是可靠性的主要威胁,因为我们不断缩小晶体管的几何形状,以实现更低的功耗和高性能的目标。本文提出的工作重点是利用自适应身体偏差(ABB)对NBTI效应建立耐受性的NBTI检测方案。在该方案中,片上监视器检测电路阈值电压的变化,通过提供给晶体管的体偏电路产生相应的自适应体偏。通过对芯片上的晶体管施加有限自适应体偏(ABB)电压,以VBB为零,即无体偏(NBB)进行了仿真,并通过在包括电流比较多米诺(CCD)在内的一系列多米诺逻辑电路上实现所提出的方法,计算了相应的功率和延迟。我们通过适当地分配电源电压来减轻延迟问题的增加,以便即使在以非常低的功率净空为代价运行10年之后也能持续满足延迟规格。在SILVACO EDA工具中,采用BSIM4v4.7模型和32nm预测技术模型,在2 GHz频率和0.9V标称电源电压下进行了仿真。所提出的方法已在32位和64位OR门以及32位比较器上实现,结果值得注意。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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