NBTI detection methodology for building tolerance with respect to NBTI effects employing adaptive body bias

Abstract

The nanometre technology is different fundamentally from its predecessors as it is exposed to a wide variety of new effects that are induced on the transistor chips. NBTI is one degradation effects in the reliability regime. It plays significant role as it leads to severe performance degradation. Ageing in pMOS transistor takes place due to Negative bias temperature instability (NBTI) which is the major threat to reliability as we scale down the transistor geometries consistently towards our objective for less power consumption coupled with high performance. The work presented in this paper focuses on NBTI detection scheme for building tolerance with respect to NBTI effects employing Adaptive Body Bias (ABB). In this scheme, an On-Chip monitor detects the change in threshold voltage of the circuit to generate corresponding adaptive body bias by the body biasing circuit which is supplied to the transistors. The simulations have been carried out taking VBB as zero, i.e., No Body Bias (NBB), by applying a finite adaptive body bias (ABB) voltage to the transistors on the chip & their corresponding power and delay have thus been calculated by implementation of the proposed approach on a host of domino logic circuits which include Current comparison domino (CCD). We have mitigated the rise in delay problem by suitably allocating a supply voltage so that the delay specifications are continuously met even after a time span of 10 years of operation at the cost of very low power headroom. Simulations have been performed using the BSIM4v4.7 model & 32-nm predictive technology model in SILVACO EDA tool at a frequency of 2 GHz and nominal supply voltage of 0.9V. The proposed approach has been implemented on 32-bit & 64-bit OR gates and also on 32-bit comparator and the results has been noteworthy.