S. Sun, P. Tsui, B.M. Somero, J. Klein, F. Pintchovski, J.R. Yeargain, B. Pappert
{"title":"A 0.4 micron fully complementary BiCMOS technology for advanced logic and microprocessor applications","authors":"S. Sun, P. Tsui, B.M. Somero, J. Klein, F. Pintchovski, J.R. Yeargain, B. Pappert","doi":"10.1109/IEDM.1991.235418","DOIUrl":null,"url":null,"abstract":"A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5 mu m logic and microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n/sup +//p/sup +/) gate CMOS process flow. Using a pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi/sub 2/ Schottky barrier diode devices formed during the titanium self-aligned silicide process are available for various circuit applications. Stacking of the tungsten-plug contacts and vias is allowed in the multilevel metallization module. A process window analysis has also been performed to derive the optimal device design targets. Compared with the CMOS counterpart, approximately 40% speed improvement (at 3.3 V V/sub cc/) in a 68030 critical path has been demonstrated using this logic BiCMOS technology.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"42 1","pages":"85-88"},"PeriodicalIF":0.0000,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 1991 [Technical Digest]","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1991.235418","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19
Abstract
A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5 mu m logic and microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n/sup +//p/sup +/) gate CMOS process flow. Using a pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi/sub 2/ Schottky barrier diode devices formed during the titanium self-aligned silicide process are available for various circuit applications. Stacking of the tungsten-plug contacts and vias is allowed in the multilevel metallization module. A process window analysis has also been performed to derive the optimal device design targets. Compared with the CMOS counterpart, approximately 40% speed improvement (at 3.3 V V/sub cc/) in a 68030 critical path has been demonstrated using this logic BiCMOS technology.<>