Gate-first implant-free InGaAs n-MOSFETs with sub-nm EOT and CMOS-compatible process suitable for VLSI

Abstract

We have demonstrated the first InGaAs MOSFETs with sub-nm EOT featuring a gate-first implant-free process compatible with VLSI. At LG = 65 nm, these devices are among the best reported ones in terms of electrostatic integrity but they suffer from a large access resistance related to a large gate-to-source/drain spacing. Future work will focus on scaling this spacing in the 5 nm range in order to achieve the desired on-performance.