4H-SiC Tapered-Gate MOSFET with Low ON-resistance and Hight Current Density

Abstract

In this paper, we developed a tapered-gate SiC VDMOSFET. The upper part of the gate of the new structure is vertical structure, and the lower part is V-shaped structure. In addition, there are also two P+ shielding layers on both sides below the gate. Simulation results reveal that the special structure is more conducive to the flow of electrons to the drift region, and the P+ shield can also protect the gate dielectric layer in the reverse blocking. In the optimized structure, the specific ON-resistance of the device reduced by 12.1%, and the current density increased by 46.6%. The figure of merit (FoM = V2BV/Ron) is 1.27 kV2/mΩ.cm2. The tapered-gate SiC VDMOSFET we designed can obtain higher current density in a smaller area, low ON-Resistance and high breakdown voltage.