First run S-DMB MMIC low noise amplifier

Abstract

This paper reports on the simulation steps needed to design a GaAs MMIC LNA for S-DMB on-board satellite applications in only one fabrication iteration, which achieves a noise figure <; 1.3 dB and gain> 28 dB for applications from 1.95 to 2.3 GHz. In addition, the amplifier obtains a high linearity with an OIP3 of 20.7 dBm and PldB of 6 dBm over a 1.95-2.3 GHz bandwidth. Availability of accurate library simulation models and the use of ADS co-simulation scheme permit us reducing design time and more importantly obtaining a first run working chip.