Heterogeneous Multi-core Architectures

Q4 Engineering
T. Mitra
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引用次数: 27

Abstract

Transistor count continues to increase for silicon devices following Moore’s Law. But the failure of Dennard scaling has brought the computing community to a crossroad where power has become the major limiting factor. Thus future chips can have many cores; but only a fraction of them can be switched on at any point in time. This dark silicon era, where significant fraction of the chip real estate remains dark, has necessitated a fundamental rethinking in architectural designs. In this context, heterogeneous multi-core architectures combining functionality and performance-wise divergent mix of processing cores (CPU, GPU, special-purpose accelerators, and reconfigurable computing) offer a promising option. Heterogeneous multi-cores can potentially provide energy-efficient computation as only the cores most suitable for the current computation need to be switched on. This article presents an overview of the state-of-the-art in heterogeneous multi-core landscape.
异构多核架构
按照摩尔定律,硅器件的晶体管数量继续增加。但是Dennard缩放的失败将计算社区带到了一个十字路口,在这个十字路口,功率已经成为主要的限制因素。因此,未来的芯片可以有多个核心;但只有一小部分能在任何时间点被打开。在这个黑暗的硅时代,芯片领域的很大一部分仍然是黑暗的,这需要对架构设计进行根本性的反思。在这种情况下,异构多核架构结合了功能和性能方面的处理核心(CPU、GPU、专用加速器和可重构计算)的不同组合,提供了一个很有前途的选择。异构多核可以提供潜在的节能计算,因为只需要打开最适合当前计算的核心。本文概述了异构多核领域的最新技术。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IPSJ Transactions on System LSI Design Methodology
IPSJ Transactions on System LSI Design Methodology Engineering-Electrical and Electronic Engineering
CiteScore
1.20
自引率
0.00%
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0
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