Reliability of large die ultra low-k lead-free flip chip packages

Abstract

With the industry movement towards lead-free solders and advanced silicon process nodes with ultra low-k dielectrics, flip chip packaging is faced with significant assembly and reliability challenges. Since lead-free solder bumps are brittle, they can easily crack without adequate support from the underfill material during thermal stress. Lead-free solder bumps have less solder fatigue resistance compared to tin-lead eutectic or high-lead bumps and require higher Tg underfills for protection. However, the higher Tg underfill and the higher reflow temperature needed for lead-free bump assembly will increase die stress and package warpage. Since lower k dielectric materials have lower mechanical strength and lower adhesion than the dielectric materials used for prior silicon generations, the high stress induced by the lead-free assembly process and material set can cause delamination within the die, especially in devices with large die and large package sizes. In order to develop and qualify a reliable and robust lead-free package, care must be taken in the materials selection and optimization of the package structure. This paper discusses the effect of different factors such as underfill, substrate core, substrate pad structure, and lid design on package reliability of lead-free fine-pitch flip chip devices. It also reviews the assembly process related factors that impact the reliability of the lead-free bump and ultra low-k devices. Our studies show that a highly reliable lead-free package on organic substrate can be achieved for devices with large die and large package sizes. The reliability results for large die with different silicon nodes from 90 nm to 28 nm are presented.