A 16 GB/s, 0.18 /spl mu/m cache tile for integrated L2 caches from 256 KB to 2 MB

Abstract

A modular 256 KB advanced transfer cache tile has been developed to implement the on-die second level caches of the 0.18 /spl mu/m Intel(R) Pentium(R) III processor family. The cache tile is stepped from 1 to 8 times to form implementations from 256 KB to 2 MB. Each tile is a self-contained cache delivering a line of 32 B every 2 clock cycles at 1.0 GHz. A charge-share data sense technique overlaps the data and tag array accesses for reduced latency at lower power. Modular tiled cache design also achieves low power through hierarchical power management and reduced test time through PBIST (programmable built in self test).