Marco Racanelli, K. Schuegraf, Amol Kalburge, A. Kar-Roy, B. Shen, Chenming Hu, D. Chapek, D. Howard, D. Quon, F. Wang, G. U'ren, L. Lao, H. Tu, J. Zheng, Jinshu Zhang, K. Bell, K. Yin, P. Joshi, S. Akhtar, S. Vo, T. Lee, W. Shi, P. Kempf
{"title":"Ultra high speed SiGe NPN for advanced BiCMOS technology","authors":"Marco Racanelli, K. Schuegraf, Amol Kalburge, A. Kar-Roy, B. Shen, Chenming Hu, D. Chapek, D. Howard, D. Quon, F. Wang, G. U'ren, L. Lao, H. Tu, J. Zheng, Jinshu Zhang, K. Bell, K. Yin, P. Joshi, S. Akhtar, S. Vo, T. Lee, W. Shi, P. Kempf","doi":"10.1109/IEDM.2001.979506","DOIUrl":null,"url":null,"abstract":"A scalable SiGe NPN demonstrating Ft*BVceo product of 340 GHz-V with Ft of 170 GHz and BVceo of 2.0 V together with Fmax of 160 GHz is presented. Peak Ft is reached at a relatively low current density of 6 mA//spl mu/m/sup 2/. The device is integrated in a 0.18 /spl mu/m BiCMOS process with dual-gate MOS transistors, high voltage NPN transistors, MIM capacitors, metal resistors, and 6 layers of metal including two layers of thick Cu for improved interconnect and inductor performance.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"151 1","pages":"15.3.1-15.3.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"80","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979506","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 80
Abstract
A scalable SiGe NPN demonstrating Ft*BVceo product of 340 GHz-V with Ft of 170 GHz and BVceo of 2.0 V together with Fmax of 160 GHz is presented. Peak Ft is reached at a relatively low current density of 6 mA//spl mu/m/sup 2/. The device is integrated in a 0.18 /spl mu/m BiCMOS process with dual-gate MOS transistors, high voltage NPN transistors, MIM capacitors, metal resistors, and 6 layers of metal including two layers of thick Cu for improved interconnect and inductor performance.
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