Reconfigurable FPGA Implementation of Product Accumulate Codes

Abstract

A memory-based, pipelined, serial architecture is developed for implementing product accumulate codes in field programmable gate arrays. A three-stage pipeline structure is exploited on the min-sum decoding algorithm to achieve full utilization of instantiated resources, to reduce latency, and to increase throughput while keeping the performance degradation minimal. Different types of interleavers are investigated and the quadratic permutation polynomial based inter-leaver is shown to be the best choice in terms of implementation cost, reconfigurability and bit error rate performance. The proposed decoder implemented in Xilinx 2v3000FG676-4 chips is capable of processing one full decoding iteration for 1 encoded bit every clock. Thus regardless of the block size, throughput will be determined only by the number of iterations done while latency is linear to block size.