Evaluation of Mechanical Stress Induced During IC Packaging

Abstract

In this work the focus is on thermo-mechanical aspects of Chip Package Interaction (CPI) in flip-chip Chip Scale packages (fcCSP) packages. To minimize mechanical stress induced during flip-chip process, the laminate substrate with very low coefficient of thermal expansion (CTE) of the core material (?5 ppm/°C) is used. Mechanical stress induced in Si chip after every main assembly step is measured using the proprietary chip with integrated stress sensors and is simulated using calibrated finite element models. In particular, two flip-chip processes, i.e. Mass Reflow (MR) and Thermo-Compression Bonding (TCB) are benchmarked. The effect of application of capillary underfill (CUF) on mechanical stress is separately studied and shown to be not significant. The CPI effect of low-CTE substrate on mechanical stress is benchmarked with that induced by the substrate with conventional thermo-mechanical properties. The benefits of lowering core' CTE in terms of stress are clearly demonstrated. This is also confirmed by finite element modeling which reveals that stress induced in Si after flip-chip die attach process is very sensitive to the effective CTE of the substrate.