Fast clock-jitter simulation in continuous-time delta-sigma modulators

Abstract

A new methodology for clock-jitter simulation in continuous-time sigma-delta (/spl Sigma//spl Delta/) converters is proposed. This analysis method, based on a previously published method uses a discrete time simulator, which is more efficient than an analog simulator. Only one sample per output sample is required which reduces simulation times to a few seconds, even for large simulations. Results are compared to those obtained with time-domain state-equations integration.