ASATM: Automated security assistant of threat models in intelligent transportation systems

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mohammad Ali Ramazanzadeh, Behnam Barzegar, Homayun Motameni
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引用次数: 2

Abstract

The evolution of technology has led to the appearance of smart cities. An essential element in such cities is smart mobility that covers the subjects related to Intelligent Transportation Systems (ITS). The problem is that the ITS vulnerabilities may considerably harm the life quality and safety status of human beings living in smart cities. In fact, software and hardware systems are more exposed to security risks and threats. To reduce threats and secure software design, threat modelling has been proposed as a preventive solution in the software design phase. On the other hand, threat modelling is always criticised for being time consuming, complex, difficult, and error prone. The approach proposed in this study, that is, Automated Security Assistant of Threat Models (ASATM), is an automated solution that is capable of achieving a high level of security assurance. By defining concepts and conceptual modelling as well as implementing automated security assistant algorithms, ASATM introduces a new approach to identifying threats, extracting security requirements, and designing secure software. The proposed approach demonstrates a quantitative classification of security at three levels (insecure, secure, and threat), twelve sub-levels (nominal scale and colour scale), and a five-layer depth (human understandability and conditional probability). In this study, to evaluate the effectiveness of our approach, an example with various security parameters and scenarios was tested and the results confirmed the superiority of the proposed approach over the latest threat modelling approaches in terms of method, learning, and model understanding.

Abstract Image

ASATM:智能交通系统中威胁模型的自动安全助手
科技的发展导致了智慧城市的出现。这些城市的一个基本要素是智能交通,它涵盖了与智能交通系统(ITS)相关的主题。问题是ITS的脆弱性可能会严重损害智慧城市中人类的生活质量和安全状况。实际上,软件和硬件系统更容易受到安全风险和威胁。为了减少威胁和确保软件设计的安全,威胁建模被提出作为软件设计阶段的预防性解决方案。另一方面,威胁建模总是被批评为耗时、复杂、困难和容易出错。本研究提出的方法,即威胁模型的自动化安全助手(ASATM),是一种能够实现高级别安全保障的自动化解决方案。通过定义概念和概念建模以及实现自动安全辅助算法,ASATM引入了一种识别威胁、提取安全需求和设计安全软件的新方法。所提出的方法在三个级别(不安全,安全和威胁),十二个子级别(名义尺度和颜色尺度)和五层深度(人类可理解性和条件概率)上展示了安全的定量分类。在本研究中,为了评估我们的方法的有效性,对一个具有各种安全参数和场景的示例进行了测试,结果证实了所提出的方法在方法、学习和模型理解方面优于最新的威胁建模方法。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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