A very low power channel select filter for IS-95 CDMA receiver with on-chip tuning

T. Kuo, B. Lusignan
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引用次数: 6

Abstract

A channel-select filter with on-chip PLL tuning for CDMA IS-95 has been integrated in a 0.35-/spl mu/m digital CMOS technology. To achieve both low power and robustness, dynamic range scaling is implemented on an elliptic ladder prototype. The dynamic range scaling is based on the special requirement for the wireless receiver. A new method to analyze the trade-off between filter noise and power consumption is presented. The filter and PLL dissipate 2.9 mW and 1.6 mW from a 3-V supply, and the die area is 1.06 mm/sup 2/. The filter achieves 61 dB stopband rejection, 0.05 dB/0.2/spl deg/ I/Q gain/phase mismatch, 100 /spl mu/Vrms input-referred noise, 20 dBm IIP3, and 58 dB SFDR.
一个非常低功耗的通道选择滤波器的IS-95 CDMA接收机与片上调谐
一个具有片上锁相环调谐的CDMA IS-95通道选择滤波器已集成在0.35-/spl mu/m数字CMOS技术中。为了实现低功耗和鲁棒性,在椭圆阶梯原型上实现了动态范围缩放。动态范围的缩放是根据无线接收机的特殊要求进行的。提出了一种分析滤波器噪声与功耗权衡关系的新方法。滤波器和锁相环从3-V电源中耗散2.9 mW和1.6 mW,芯片面积为1.06 mm/sup 2/。该滤波器可实现61 dB阻带抑制,0.05 dB/0.2/spl度/ I/Q增益/相位失配,100 /spl mu/Vrms输入参考噪声,20 dBm IIP3和58 dB SFDR。
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