R. Safranek
{"title":"Intel® QuickPath interconnect overview","authors":"R. Safranek","doi":"10.1109/HOTCHIPS.2009.7478336","DOIUrl":null,"url":null,"abstract":"Presents a collection of slides covering the following topics: Intel QuickPath Interconnect; platform configuration; physical layer; link pair; transmitter discrete-time linear equalizer; coefficient search; link layer; virtual channel mapping function; message class; command insert interleave; routing layer; protocol layer; and configuration agent.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"9 1","pages":"1-27"},"PeriodicalIF":0.0000,"publicationDate":"2009-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2009.7478336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4