H. Hsiao, S. W. Ho, S. Lim, L. Wai, S. Chong, Pei Siang Sharon Lim, Yong Han, T. Chai
{"title":"Ultra-Thin FO Package-on-Package for Mobile Application","authors":"H. Hsiao, S. W. Ho, S. Lim, L. Wai, S. Chong, Pei Siang Sharon Lim, Yong Han, T. Chai","doi":"10.1109/ECTC.2019.00011","DOIUrl":null,"url":null,"abstract":"Today, Package on Package is a major trend of three-dimensional fabrication for processors and high-performance memory applications in portable applications. Package-on-Package has the benefit of a mini packaging size with multi-functionality by stacking two different packs. However, an ordinary Printed circuit board substrate Package on Package has a weak point to meet the now low profile necessary of high-performance in the thin portable application. To overcome this weak point, the package has been introduced to the market by Fan Out Wafer Level, and this structure of the package allows I/O to be within the device surface and expand through the combination of form so that they can be accommodated more FOWLP. Ultra-thin Fan-out PoP was developed using RDL-first process flow. The developed Fan-out PoP has a package size of 15 x 15 mm2 and thickness of 800 µm, and it consists of three embedded chips. The bottom package consists of a 10 x 10 mm2 processor chip assembled to under bump metallization (UBM) of the bottom RDL layers. Vertical wire-bonds are integrated into the bottom package to act as vertical through mold interconnect (TMI) to the top RDL layers. The top package consist of two 7 x 11 mm2 silicon chips assembled laterally on top of the bottom package and connected to the top RDL layer with low-loop wire-bonds. The top chips were encapsulated in epoxy mold compound to form an integrated PoP. RDL-first integration flow was used to fabricate the fan-out package whereby RDL, molding and chips assembly processes were performed on a carrier wafer to overcome warpage associated with conventional Mold-first process. The ultra-thin Fan-out PoP samples pass the reliability include the MST level 3, drop impact test and the Thermal Cycling. It also provides good thermal performance on packaging level and system level applied in mobile device.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"21-27"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2019.00011","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
Today, Package on Package is a major trend of three-dimensional fabrication for processors and high-performance memory applications in portable applications. Package-on-Package has the benefit of a mini packaging size with multi-functionality by stacking two different packs. However, an ordinary Printed circuit board substrate Package on Package has a weak point to meet the now low profile necessary of high-performance in the thin portable application. To overcome this weak point, the package has been introduced to the market by Fan Out Wafer Level, and this structure of the package allows I/O to be within the device surface and expand through the combination of form so that they can be accommodated more FOWLP. Ultra-thin Fan-out PoP was developed using RDL-first process flow. The developed Fan-out PoP has a package size of 15 x 15 mm2 and thickness of 800 µm, and it consists of three embedded chips. The bottom package consists of a 10 x 10 mm2 processor chip assembled to under bump metallization (UBM) of the bottom RDL layers. Vertical wire-bonds are integrated into the bottom package to act as vertical through mold interconnect (TMI) to the top RDL layers. The top package consist of two 7 x 11 mm2 silicon chips assembled laterally on top of the bottom package and connected to the top RDL layer with low-loop wire-bonds. The top chips were encapsulated in epoxy mold compound to form an integrated PoP. RDL-first integration flow was used to fabricate the fan-out package whereby RDL, molding and chips assembly processes were performed on a carrier wafer to overcome warpage associated with conventional Mold-first process. The ultra-thin Fan-out PoP samples pass the reliability include the MST level 3, drop impact test and the Thermal Cycling. It also provides good thermal performance on packaging level and system level applied in mobile device.
今天,包对包是一个主要的趋势,三维制造的处理器和高性能存储器应用在便携式应用。包上包的好处是一个迷你的包装尺寸与多功能堆叠两个不同的包。然而,普通的印刷电路板基板封装在封装上有一个弱点,以满足现在在薄便携式应用中高性能所必需的低轮廓。为了克服这一弱点,该封装已通过扇出晶圆级(Fan Out Wafer Level)推向市场,该封装的这种结构允许I/O位于器件表面内,并通过组合形式进行扩展,从而可以容纳更多的FOWLP。采用RDL-first工艺流程开发了超薄扇形PoP。开发的Fan-out PoP封装尺寸为15 x 15 mm2,厚度为800µm,由三个嵌入式芯片组成。底部封装由一个10 x 10 mm2的处理器芯片组成,组装在底部RDL层的碰撞下金属化(UBM)上。垂直线键集成到底部封装中,作为垂直通过模具互连(TMI)到顶部RDL层。顶部封装由两个7 x 11 mm2的硅芯片组成,横向组装在底部封装的顶部,并通过低环线键连接到顶部RDL层。顶部的芯片被封装在环氧模化合物中,形成一个集成的PoP。RDL-first集成流程用于制造扇形封装,其中RDL,成型和芯片组装过程在载体晶圆上执行,以克服与传统模具-first工艺相关的弯曲。超薄扇出式PoP样品通过了MST 3级、跌落冲击测试和热循环测试。在移动设备的封装级和系统级均具有良好的散热性能。