Influence of Gate Driver Loop Inductance on SiC MOSFET Module Turn-on Gate Voltage Oscillation in High Power Application

Abstract

High power SiC MOSFET module has been widely used in HEV/EV (Hybrid Electric Vehicle/Electric Vehicle) traction inverters due to superior dynamic and static performance. However, the fast transient characteristic and inherent parasitic parameters could result in unexpected oscillation in the SiC MOSFET gate loop. This paper comprehensively analyzes the mechanism of gate-source voltage (vgs) oscillation during SiC MOSFET turn-on. Large power loop parasitic inductance would generate drain-source voltage (vds) oscillation, which could have adverse impact on gate-source voltage (vgs) through miller capacitor according to Kirchhoff’s Laws. Furthermore, large gate inductance from copper trace on PCB could exacerbate the vgs oscillation. Finally, simulation and experimental comparison between two driver board layouts reveal the influence of gate driver loop inductance on SiC MOSFET module turn-on gate voltage oscillation and validate the proposed PCB design recommendations.