Converging Formal Verification in a High-Level Synthesis Environment

Abstract

Recent advances in silicon chip technology have facilitated the development of very dense Systems-on-Chip (SoC) and Application-Specific Integrated Circuits (ASIC). However this density has made the products often, to fail in the market window. It is widely accepted amongst the engineering community that a large proportion of development effort and delays is due to very extended, detailed, prone to bugs and repetitive low level simulations generated by attempts to cover most corner cases. This paper discusses a Formal High-level Synthesis - based verification method, that is based on high-level compile and execute of program code, and produce simulation engines from various levels in the design flow. Eventually the produced “simulators” execute and converge to the same results, since the Synthesis process is formal. The complete, and rapidimplementation flow is formal becaue the automated cycle-accurate simulator is generated from the the same formal optimized model used by the completed High-level Synthesis flow. A huge number of benchmarks from real-life applications, a few of which are discussed here, were developed and validated with the method presented in this paper and always the formal nature of the tools helped to catch all of the bugs as early as possible in the implementation flow.